1. Field of the Invention
The present invention relates to a printed wiring board where the area of the lowermost conductive layer is set greater than the area of the uppermost conductive layer when seen directly under an IC chip.
2. Discussion of the Background
Japanese Laid-Open Patent Publication No. 2007-88140 relates to an assembled printed board. In Japanese Laid-Open Patent Publication No. 2007-88140, a dummy circuit is formed on an upper or lower surface of an individual printed wiring board to equalize the ratios of remaining copper on the upper and lower conductive layers of the individual printed wiring board. The entire contents of this publication are incorporated herein by reference.